1. Field of the Invention
The present invention relates to a read only memory (ROM), and in particular to improvements in the circuitry and methodology of the subcircuits included within a very large scale integrated (VLSI) ROM.
2. Description of the Prior Art
As shown in FIG. 1, the overall structure of a prior art ROM is typically comprised of an input buffer circuit, an address transition detector circuit (ATD), an X and Y decoder circuit, a sense amplifier for reading the memory cells. A plurality of memory cells coupled to the input buffer and accessed through the X and Y decoder with their output completed to the sense amplifier, and an output buffer circuit having its input coupled to the output of the sense amplifier. The function of the input buffer is to convert a TTL level signal into a voltage level compatible with the ROM when an address signal is received at the ATD circuit. The function of the address transition detector circuit is to detect address transitions from the output of the input buffer in order to generate appropriate timing signals within the ROM. The X and Y decoders decode an address to select a predetermined memory cell within the array. The sense amplifier reads the data stored in the memory cell. The output from the sense amplifier is then buffered to the output circuit for a TTL level output. Such prior art architectures are prone to several limitations as discussed below.
Prior art output buffer circuits have experienced slow switching speeds in the NMOS output transistors. For example, as described in the IEEE Journal of Solid State Circuits, Vol. 23, No. 5, 1988 at pages 1054 1058, an output buffer circuit suppresses the peak of current flowing from an output pin by temporarily setting its output at an intermediate potential between the high and low logic levels. However, since the output is temporarily set at an intermediate potential, current flows through the output circuitry if a CMOS device is provided as the input of the next stage. In the circuit described in the1988 IEEE Solid State Circuits Conference Digest of Technical Papers, pages 120-121, a bias signal is applied to an NMOS transistor in the final inverter stage of the output buffer circuit through a coupling transistor. The bias voltage is applied to a coupling transistor. Since the bias voltage is fixed between zero volts and the supply voltage, the switching speed of the final stage, NMOS transistor is increased. The increase in switching speed is utilized to suppress the peak current which flows from the output pin to ground when the output level switches from a high to a low logic level. However, since the switching rate of the NMOS transistor is increased, excessive time is required to convert the output to a high output level.
Among the efforts currently being made in the art to produce larger and denser semiconductor devices, is the use of dynamic circuits for constructing larger scale and faster memories. However, a conventional dynamic circuit has a data hold period in the buffer, that is, the period during which data must be held regardless of the circuit's gated diffusion capacity. Therefore, due to pattern layout architecture, performance during hold periods may be erratic. If the signal is affected by coupling noise input through a gate, the transistor may enter a half-on state, if not malfunctioning altogether, because the gate voltage is floating and not driven. This in turn leads to the emission of hot electrons. Hot electrons can affect the reliability of the array and can be substantial where the circuit is highly miniaturized. Therefore, what is needed is a dynamic circuit which is not affected by these coupling noises.
Refer briefly to FIG. 25 which shows a prior art circuit used to deal with noise in an output buffer. Noise is reduced by applying an intermediate voltage or bias to the gate of a transistor 350 when the input signal, IN, changes from the logic low to the logic high to cause transistor 352 to enter a half-on state which would gradually drain the current from the output port to ground. This increases the buffer's time delay when the process variations, device temperatures and/or voltage levels are in their slowest state.
The usual methods to generate a bias level is to generate an analog voltage that varies with temperature and process conditions and that allows some compensation in response to those conditions. In using these prior methods it is difficult to adjust the voltage level. The solution suffers from the limitation and the compensation tends to slow down to the slowest circuit part, thereby causing a substantial degradation in the worse case speed specification in the circuit. It is also important to note that when the circuit is in its slowest condition, compensation may not be necessary and may in effect be detrimental.
In this case, if the bias voltage is fixed at an intermediate level, delay of the output buffer becomes excessively large even though the noise in the output buffer is reduced. What is needed then is a means and method of solving the problem with a bias voltage supply circuit which can adjust the bias voltage, taking process variations into consideration as well as circuit speed reaction to voltage level.
Therefore, it is an object of this invention to provide a ROM circuit which overcomes each of the above-discussed shortcomings of the prior art.
It is an object of the invention to provide an output buffer circuit which is not characterized by a high switching current and still has a fast switching speed.